Advanced packaging techniques such as system-in-package (SiP), fan-out wafer-level packaging (FOWLP), 3D die stacks, etc. have been around for over a decade, yet with any other EDA design tool, it is still a tedious, time consuming, and error-prone process to implement these designs. It seems surprising that there are so few reliable EDA solutions out there, but CR-8000 Design Force is definitely the tool to look to when tackling advanced package design! Take a look below and see why.

CR-8000 Design Force was architected as a hierarchical printed circuit board and integrated circuit package design database. The image below shows an example of a package-on-package (PoP) design. The lower package contains two ASICs, while the upper package has six memories. You can easily switch from substrate to substrate and make design changes. Pin swaps at the shared pins are passed seamlessly between the designs.

The natural hierarchical and 3D architecture of this tool makes it simple to create just about any type of advanced package design you might be able to imagine. At the recent IWLPC conference in San Jose, Samsung presented on Fan-out Panel Level Packaging. CR-8000 Design Force is the natural choice for this type of design as it doesn’t require re-tooling (or re-coding) to make it work!

CR-8000 Design Force enables co-design between all parts of the design in an intuitive flow, not simply IC package co-design functionality in a separate design environment, but co-design natively built into the software’s DNA. With CR-8000 Design Force, you don’t need a separate co-design tool. It provides package-to-package co-design; IC-package; package-to-board; board-to-board; board-on-board; board-to-assembly panel; co-analysis between layout and analysis tools, and data exchange with 3rd-party EDA vendors. The image below illustrates the “co-design is everywhere” concept.

Examples

Let’s take a look at some specific examples of design capabilities in CR-8000 Design Force.

IC-Package Co-design

The first example is an IC-driven co-design scenario in which the package design team imports the I/O driver placement through LEF/DEF import, creates a bump pattern for the IC and optimizes the bump pattern and the package connectivity in Design Force. The IC design is all done in a native OpenAccess environment (inside Design Force, no less!).

Pin assignments are made to the package, and optimization of pin assignments operates in a bidirectional manner between the IC and the package.

The final result is a clean pathway from I/Os to package balls. Any changes to the die are exported to a DEF file.

Package-on-Package Clearance and Collision Checks

The second example is a Package-on-Package (PoP) design flow. It demonstrates collision and clearance checks between devices on the top and bottom packages of a PoP design. These components are imported either from LEF/DEF, or are fixed components in a library. In the movie, the top package has a memory device on its underside, and the bottom package has an ASIC on the top layer. The movie shows collision and clearance checks between the devices. This functionality is especially useful in designs with many passive components on the facing boards to ensure collisions do not occur when the part is assembled.

Daisy Chain Test Chip

The final example illustrates the creation of a daisy chain test configuration between two packages and between a package and a die in a PoP design. A daisy chain test configuration is a stitching of pins between two (or more) different components to provide a nearly zero-Ohm path between a set of pins and is used for a variety of tests to validate and improve the assembly process. The image below shows a simple example of two daisy chains (daisy chains 1 and 3) between two packages in a package-on-package configuration. It also shows a single daisy chain (daisy chain 2) between a flip-chip die and the bottom package.

Creating this type of netlist is a tedious and error-prone process with most tools. However, because CR-8000 Design Force is naturally a 3D, hierarchical design system, it provides an easy-to-use utility to create and visualize complex daisy chain configurations. The chain is created or modified by selecting a set of pins and running the command. The netlist for both sets of pins is created (or updated) and the routing for both substrates is created.

The first example below shows a 2D view of a PoP design with a single flip chip. There are four daisy chains between the two packages around the perimeter, and there are 15 daisy chains between the die and the bottom package. This design could take days or weeks to complete, but in CR-8000 Design Force, it was a matter of minutes for all chains and routing to be completed!

This next image is a close-up of the 2D view of a few of the chains.

This last image is a 3D view of the chains. Note that only the metal wires are shown, and wires are not shown to scale.

Summary

CR-8000 Design Force is a powerful environment that provides hierarchical design layout and assembly, 3D and 2D design views that enable the assembly of complex packages and PCB configurations in one database, and in one design canvas. Because of this, creating a package-on-package fan-out wafer level design, or a complex PCB, package, and die stack up is rather simple to do. Complex daisy chain designs are quickly completed. Memories in a top package can easily drive the pinout of ASICs in a bottom package. Connectors on a PCB can drive net assignment to die pins in a die stack. 2D and 3D modes provide an intuitive, dynamic window into the layout of the design. Collision checks and clearance checks provide a view into the 3D space of your design. Design Force is the tool of choice for anyone designing advanced packages of all types.

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Overcoming Crosstalk

The higher data rates of DDR4 increase the edge rate which in turn increases the propensity for crosstalk. A general rule of thumb is to space out adjacent signal traces at least three times the trace width in order to minimize coupling effects. But it’s often difficult to implement such large trace spacing, especially on smaller PCBs such as those used in smartphones. This conundrum is increased by the fact that SDRAM uses a source synchronous clocking scheme in which all the signals in each signaling group propagate in one direction at the same time. In cases where large trace spacing cannot be achieved, the next best choice is typically to route these traces on stripline – inner PCB layers – instead of microstrip – the outer layer. This is because one side of microstrip does not have a power plane, resulting in greater dispersion of electromagnetic waves which in turn leads to a greater propensity for crosstalk to occur.

Avoiding Vias When Practical

But nothing is simple in PCB design and routing on inner layers can also create complications when DDR4 signals travel through vias from one layer of a PCB to another. Capacitance and losses in the vias can produce signal integrity problems, especially in the short stubs formed by the extension of the vias plating through to the other side of the PCB. One approach to address this problem is to minimize layer changes by routing mainly in the outer layers to avoid layer changes. But since, as mentioned earlier, routing on the outer layer increases the tendency towards crosstalk, other measures may be necessary. For example, backdrilling with numerically controlled drills to reduce the via stub length can significantly lower the bit error rate of the interconnect.

Tune the Silicon to the Board

Cases where designers have control over the silicon provide an additional avenue to address potential DDR4 problems. Devices such as field programmable gate arrays (FPGAs) enable engineers to move pins around to reduce trace lengths. While ICs, packages and PCBs are typically designed with point tools whose interface requires time-consuming manual processes, a new integrated 3D chip/package board co-design environment enables engineers to see the IC, package and PCB simultaneously in one view to optimize tradeoffs between the pin placement and PCB routing, among other things. This new approach makes it much easier to, for example, swap pins between banks, to achieve better length control.

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