Applying a transmission line model based on the telegrapher’s equations (as typically common in signal integrity considerations except for when considering extremely high data rates, e.g., SERDES channels), one often used the general expression for the characteristic impedance of a lossy transmission line is:

where:

R = the resistance per unit length, considering the two conductors to be in series,

L = the inductance per unit length,

G = the conductance of the dielectric per unit length,

C = the capacitance per unit length,

j = the imaginary unit, and

w = is the angular frequency

As for the transmission line model, it was shown in part 1 of this blog but is worth showing again here as a reminder (see figure 1).

Although an infinite line is assumed, the characteristic impedance is independent of the length of the transmission line (as all quantities are per unit length). Hence, the electrical behavior of a digital signal is mainly determined by the geometry of the conductor. It is, therefore, possible to compute the above parameters and derive impedance and signal velocities from them. NB: the material characteristics of the insulator material (=dielectrics) must also be known.

If a certain impedance is to be achieved for given track dimensions (as specified by the PCB manufacturer), then by varying the dielectric height it is possible to achieve the required impedance value (see figure 2). Alternatively, the developer may also vary the dielectric material and thus influence the impedance by controlling the L and C characteristics. NB: for simplification, we are considering a lossless case; i.e., we neglect the frequency-dependent parameters R and G for the moment and assume that there is no line resistance and no dielectric loss.

As the dielectric constant er primarily influences the propagation of the E and H fields and the current flow through the conductor, it is obvious how important the surrounding medium (the dielectric material) is on the achieved impedance and the signal propagation.

If there is no signal reference (ground or supply layer) in the immediate vicinity of the signal line, the signal return path is somewhat variable and the impedance value of the transmission line can get very high. Worst case it can get close to that of a single line in air (ZL = approximately 377W).

Due to the varying input resistances and the different switching behavior of the ICs on a board, various impedance targets need to be matched when designing a large PCB. This makes it crucial for the developer to know about the design constraints resulting from the layer stack structure (see figure 3) during the design process.

Common engineering practice is to build, over time, a library of known layer-stacks with defined impedance configurations, so that developers can relate to set values and not have to develop a new layer structure every time.

Visualizing the structure in 2D (or in  3D) helps to takes the pain out of handling increasing design complexity. NB: in particularly challenging high-speed designs, it is a common (but costly) practice to order impedance-controlled printed circuit boards – as all the design constraints and calculations were made during the design. Also, please note, that impedance-controlled PCBs are not produced using higher accuracy processes; as the ‘control’ implies the creation of test coupons for all possible impedance situations on all layers and enhanced testing whether the target is met or not. Proper impedance planning early in the design phase can help save the (typically) 25% premium you’ll pay for impedance-controlled boards.

The calculation of impedances (especially when done by the formulas employed by web-based design tools) usually takes the assumption of a rectangular cross-section of the finished circuit trace with a perfect current return path. However, the real cross-section is more likely to be a polygon approaching a trapezoidal shape; sometimes crosses gaps in the reference layer underneath (current return) and can vary widely from board manufacturer to board manufacturer.

This then raises the question whether the assumption of a rectangular cross-section for an impedance calculation is accurate enough – and will signal integrity to be compromised by this non-perfectly-shaped cross-section? The field solver can take into account the etching changing the trace geometry, and they can detect situations where the track shows a so-called discontinuity as well.

As mentioned in part 1 of this blog, to ensure a reflection-free signal, high-speed nets require impedance matching. This means that the driver (output resistance), the transmission line and the receiver must show as little as possible (and ideally no) impedance difference values. In contrast, unmatched signals then show significant distortion as shown in figure 4.

However, routing may cause other issues. For instance, branches in topologies (see Figure 5) can create a voltage divider and produce therefore a reflection point – despite a supposed ideal adaptation of the same resistance in all legs (perfect matching requires we use Kirchhoff’s law for resistance in parallel).

Do you need to be 100% on target? Yes and No

In digital electronics, data and information are often exchanged point-to-point between two components. It is mandatory, that information is transmitted without being distorted or delayed.

It can be concluded that the signal integrity of critical signals must be ensured; hence, impedance control is the first step to do so. The decision of whether a signal still arrives with sufficient quality must be answered on the basis of the circuit characteristics and the component specifications. In many cases, components can detect the switching information even if the signal is slightly distorted. Alternatively, modern silicon can be programmed via hardware settings to significantly improve the signal quality at the receiver. If available, this option should always be used when working ‘close to the limits’ with regard to signal integrity budgets. Alternatives can be explored through signal integrity simulations.

To judge the effect on the signals, you must consider the two major reasons for impedance matching:

• Control the delay
• Reduce reflections and attenuation.

In the fan-out area of high-pin BGAs, traces are often ‘necked-down’ for routing space reasons between the BGA balls, which creates an impedance mismatch (i.e., a reflection situation). A typical 50Ω trace on an inner layer has a propagation delay of about 6 ns per m. If this transmission line is part of a differential pair and traverses (for instance) a BGA breakout region and has a ±30% impedance mismatch (i.e. 65Ω) over a length of 3 cm, the signal transit time will be delayed by 6ps. This will create a small phase shift even at 3GHz. Not too much of a concern. The bigger the issue is the risk of reflections.

Often, an exact adaptation of the impedance is not possible (and often unnecessary). Smaller mismatches are often still acceptable, as the proper logical switching of the signals is ensured by the semiconductors’ switching tolerances.

However, no general design rule should be inferred from this. In such cases, it is more important to minimize the deviations of the impedances – and of course to be aware of the consequences. SI simulations tools like the CR-8000 Analysis Module will reveal their virtual prototyping power in such situations.

An example of the real-life impact of matched impedance is shown in figure 6, where the switching behavior of a DDR3 data signal (point-to-point, the receiver only) is shown and where the memory vendor (Micron) demanded an impedance value of 50Ω.

During the final verification of the PCB, the designer controlled all traces of the DDR3 interface using the Zuken SI simulator, considering all possible manufacturing tolerances (20% was stated by the board manufacturer). When reaching the upper tolerance boundary of 60Ω, proper switching could not be ensured (a serious ring-back below the threshold is visible, yielding a timing error) whereas, closer to the lower boundary (between 42 and 45Ω) signal behavior is best.

This shows the strength of concurrent simulation as part of the design process and the benefits of conducting investigations on the virtual prototype.

Conclusion

For the cost-effective development of high-speed printed circuit boards, it is important to not only know the different options of impedance-controlled design but also to know (or define) the necessary and achievable tolerances.

A proven approach is to constrain up-front, design to target impedances and to optimize the PCB. The effects of an impedance mismatch must be known and understood and, in this respect, the use of simulation tools and virtual prototyping is key to success. In addition, close collaboration with the PCB manufacturer – during the early stages of your project – is highly recommended. Indeed, the CAM departments of your PCB manufacturer can often provide proper indications to solve all impedance-related design questions. However, designers are advised not to hand over the control of impedance issues to external parties.

Learn more

• Blog: Inside Signal Integrity: Impedance Control, part 1
• Zuken Blogs about Signal Integrity
• Zuken Blogs about Power Integrity

The post Inside Signal Integrity: Impedance Control – Part 2 appeared first on English.

In this, the first of a two-part blog, we’ll go back to the basics of impedance/impedance control and consider what influences line impedance. In part two, we’ll set about controlling it.

To ensure proper signal integrity for a PCB that incorporates high-speed digital devices, it is essential to control the transmission line impedance.

So, what do I mean by ‘proper signal integrity’. I refer to signal quality/purity that at the end helps to meet the timing requirements of high-speed digital devices. Increasingly, circuitry features signals with ultra-fast switching times, which must comply with ever-tightening design-constraints like skew matching or setup and hold requirements.

One of the basic constraints – the ‘mother’ of all high-speed constraints, if you will – is line impedance; be it single-ended or differential (Z_diff). Where high-speed digital ICs are concerned, the OEM or the used standard/protocol will specify the required impedance. Figure 1 shows some examples.

Alternatively, you can try to calculate the desired line impedances yourself. For this, there are a number of formulae that can be used – two of which are shown in figure 2 – that provide varying degrees of accuracy.

Common to all is that they marry your design elements (e.g., track lengths and widths, layer stacks etc) with the physical properties of the intended manufacturing process (predominantly the materials being used). Such formulae can yield esp. for single-ended structures rather accurate results – but there are not suitable for coupled situations (like differential pairs) – here more advanced techniques like field solvers are required.

For many PCB designers, dealing with impedance is their first and sometimes only contact with the complex world of high-speed design.

Transmission line impedance

The electrical behavior of a signal line is, in principle, dictated by conductor geometry. Once you know the material constants of the surrounding media, you can calculate the dielectric constant, er, which gives the electrical parameters of a line. The trace width, together with the height of the trace, determines the geometry of the trace.

Every electrical conductor comprises capacitance, inductance, and a frequency-dependent ohmic resistance (see figure 1 showing a common used electrical equivalent circuit of a transmission line segment). With increasing frequencies, the parasitics and the transmission line impedance cannot be ignored, or it will influence and may distort the signal. As a consequence, the signal becomes an active interconnect instead of a passive connection.

A change in the conductor width always means a change to the cross-sectional area and so has an impact on the maximum current and thermal behavior. In applications where very high clock speeds or data rates, and relatively long electrical line lengths are required (e.g., backplanes), ohmic resistance can also play an important role.

However, the occurrence of a change in the electrical behavior of a conductor through varying its height is relatively rare. Typical multi-layer stack-ups use conductor heights of between 17 and 36μm. These are mainly determined by mechanical constraints, such as the overall board thickness. It should be mentioned that the manufacturing process will deform the ideal rectangular (cross-sectional) shape of the track (etching effect).

Back to basics

The characteristic impedance or surge impedance (usually written Z₀) of a uniform transmission line is the ratio of the amplitudes of voltage and current of a single wave propagating along the line; that is, a wave traveling in one direction in the absence of reflections in the other direction. Characteristic impedance is determined by the geometry and materials of the transmission line and, for a uniform line, is not dependent on its length.

The standard unit (SI unit) of characteristic impedance is Ohm (W). The characteristic impedance of a lossless transmission line is purely reactive, with no real component. Energy supplied by a source at one end of such a line is transmitted through the line without being dissipated in the line itself. A transmission line of finite length (lossless or lossy) that is terminated at one end with an impedance equal to the characteristic impedance appears to the source like an infinitely long transmission line and produces no reflections. (Source: Wikipedia).

What does that mean for a PCB designer in terms of signal integrity?

It can be shown that an equivalent definition of characteristic impedance is as follows: the characteristic impedance of a line is that impedance which, when terminating an arbitrary length of the line at its output, will produce an input impedance equal to the characteristic impedance. This is so because there is no reflection on a line terminated in its own characteristic impedance (as per the above Wikipedia definition).

The characteristic impedance of a transmission line is determined by the following factors:

• The trace geometry (trace width and height);
• The distance between the signal layer and the current return path; and
• Dielectric constant, ε_r

To achieve the desired impedance and to match the required tolerances, PCB designers tend to work closely with the PCB manufacturer.

Based on the favored stack-up and the PCB layout demands, a proper impedance calculation method should be chosen. Guesswork and hope are not good engineering practices here, and the impedance targets for at least all critical signals must be determined before routing begins.

In today’s PCB manufacturing processes, tolerances of between 5 and 10% for impedance values can be achieved with: appropriate material selection; proper design of the layer stack structure (see figure 4); trace geometry planning (including any influence the etching process may have) and careful layout.

In summary, line impedance plays an even more critical role in today’s high-speed digital designs. Ideally, a transmission line should be terminated at on end with resistance in relation to its characteristic impedance to minimize signal reflections.

In part 2 of this blog, I will discuss how best to achieve line impedance control and outline the ramifications of tolerances in the manufacturing process.

Learn more

• Zuken Blogs about Signal Integrity
• Zuken Blogs about Power Integrity

The post Inside Signal Integrity: Impedance Control – Part 1 appeared first on English.

Even though power integrity strategies are now discussed on a daily basis, power distribution design is still a third order design aspect, done late in the design. It involves often a “design-by-hope” approach doing a copper pouring of the power-templates, and additionally sprinkling the board with decoupling capacitors. Such traditional methods of designing complex PCBs, and their power distribution systems (PDS) in particular, cost companies time and money in both the design and manufacturing stages.

But it doesn’t have to be this way

Here is an approach, using Zuken’s embedded power integrity solution in CR-8000 Design Force. The aim is to reduce unnecessary power layers in the board and to eliminate panic approaches, such as adding ‘fear capacitors’. The core concept behind this concurrent analysis solution involves designing the power distribution system (PDS) first to guarantee positive power integrity results as early as possible.

It’s all relative – EMC and the PDS

The overall performance and EMC behavior of electronic equipment is not only determined by the design of the circuitry and geometry of the layout, but also by the PDS. Parasitic noise voltages on the power/ground system, caused by the fast switching of currents from integrated circuits (ICs), can lead to malfunctions and significant increases in electromagnetic emissions. High-speed components that utilize numerous complex high-pinout ICs, like FPGAs and CPUs operating on multiple voltage rails, add fuel to the fire.

As these ICs become more of a commodity in electronics applications, the fight for the board real estate required to successfully transmit gigabit-speed signals gets more aggressive. So the traditional approach to address SI, PI and EMC in silos, disconnected from the board layout, is no longer appropriate.

Small changes – dramatic impact

The smallest change in component selection, placement, routing or power/ground plane design can have a dramatic impact on the overall system performance. The PDS is critical. It is a the workhorse of the system providing operational voltage; supplying the current demands of all the active circuits; providing reference levels; implementing the current return paths for all the signal loops; and compensating for external noise. So the PDS needs to be designed rather than created by simply flooding layers with copper.

Other issues that reinforce the need to design rather than simply create, include the need to provide charge over a wide frequency range, from low (e.g., system peripherals like disk drives) up to high frequencies, getting into the GHz range. The ongoing lowering of supply voltages and noise margins of today’s ICs make the design of the PDS, and definition of its target impedances, a major design challenge.

Designing the PDS right-first-time

Back when designers only had to deal with a few voltages, there was little need for extensive design to create a PDS. The overall board design process would start with the placement of ICs and routing of regular traces, followed by a definition of the area allocated for the PDS. The final stage in this process was simply to connect all the ICs to the PDS.

The increased complexity and density of boards means that this simple approach is not as effective as it once was. The final stage is no longer just about connecting from A to B; purely because it is no longer physically possible. With today’s complex boards, the approach has been to incorporate different layers for different voltages. But this has a negative knock-on impact on the cost of both design and manufacture. Alternatively, extra ‘fear capacitors’ can be placed on a board in the final stages of design to achieve power integrity. Again, this increases cost in both additional components and manufacturing. The recommended option that eliminates the requirement of extra layers or ‘fear capacitors’, involves designing the PDS first, and then placing the other components around it – ensuring power integrity from stage one.

Effective PDS design

Fast analysis methodology including what-if capabilities for concurrent power integrity analysis is required. Full wave 3D solutions that can provide highly accurate results are unfortunately not applicable within the design process of most electronic systems, where time to market and time to volume are key. A systematic approach that provides design arbitration to achieve a balance between conflicting constraints is essential.

The concept is simple: optimize analysis time invested to achieve reliable decision making results. In order to accomplish this, the new methodology requires that the available data is utilized throughout the design process, and that design consistency is maintained at all levels. EDA tools must manage the various design constraints with the ability to arbitrate between conflicting requirements.

Concurrent design

A concurrent design solution, such as Zukens CR-8000, integrates the power integrity methodology into the layout phase of the design process. It also ensures that a consistent set of design constraints, including power distribution and de-coupling requirements, is maintained throughout the design flow. Integrated EMC and power integrity verification is available within CR-8000 Design Force – where constraints conflict, this approach enables them to be resolved early in the design process. Features like adding virtual decoupling capacitors for conducting what-ifs, and parametric studies, and a dedicated solver to compute current distribution and DC voltages, complement the solution.

Example – car navigation system

As an example, consider a car navigation system that includes a very small board with a fixed form factor. The unit needs to fit into the radio slot within the car. Boards like these feature high density IC technology such as FPGAs and CPUs, all with fast low power DDR3 (LPDDR3) memories and high-speed data links. The board also has to conform to a set power supply environment defined by the car manufacturer, and must comply very strict EMC limits. The challenge is then to fulfil all these demands to ensure power and signal integrity, and guarantee EMC. The PDS is designed first, and all the components are then placed and routed using the initial PDS design. Just as signal integrity requirements for high-speed systems require designers to organize the topology of connections to achieve clean signals, the architecture of power distribution systems must now be deliberately designed to prevent power integrity problems. But by using advanced design techniques (such as those in CR-8000) and using the concurrent analysis capabilities for SI and PI, costly extra board layers and increased component and manufacturing costs can be avoided.

Find out more about Power Integrity in Zuken’s CR-8000

The post Mastering Power Integrity: First Get Your Power Distribution System Right appeared first on English.