Applying a transmission line model based on the telegrapher’s equations (as typically common in signal integrity considerations except for when considering extremely high data rates, e.g., SERDES channels), one often used the general expression for the characteristic impedance of a lossy transmission line is:

where:

R = the resistance per unit length, considering the two conductors to be in series,

L = the inductance per unit length,

G = the conductance of the dielectric per unit length,

C = the capacitance per unit length,

j = the imaginary unit, and

w = is the angular frequency

As for the transmission line model, it was shown in part 1 of this blog but is worth showing again here as a reminder (see figure 1).

Although an infinite line is assumed, the characteristic impedance is independent of the length of the transmission line (as all quantities are per unit length). Hence, the electrical behavior of a digital signal is mainly determined by the geometry of the conductor. It is, therefore, possible to compute the above parameters and derive impedance and signal velocities from them. NB: the material characteristics of the insulator material (=dielectrics) must also be known.

If a certain impedance is to be achieved for given track dimensions (as specified by the PCB manufacturer), then by varying the dielectric height it is possible to achieve the required impedance value (see figure 2). Alternatively, the developer may also vary the dielectric material and thus influence the impedance by controlling the L and C characteristics. NB: for simplification, we are considering a lossless case; i.e., we neglect the frequency-dependent parameters R and G for the moment and assume that there is no line resistance and no dielectric loss.

As the dielectric constant er primarily influences the propagation of the E and H fields and the current flow through the conductor, it is obvious how important the surrounding medium (the dielectric material) is on the achieved impedance and the signal propagation.

If there is no signal reference (ground or supply layer) in the immediate vicinity of the signal line, the signal return path is somewhat variable and the impedance value of the transmission line can get very high. Worst case it can get close to that of a single line in air (ZL = approximately 377W).

Due to the varying input resistances and the different switching behavior of the ICs on a board, various impedance targets need to be matched when designing a large PCB. This makes it crucial for the developer to know about the design constraints resulting from the layer stack structure (see figure 3) during the design process.

Common engineering practice is to build, over time, a library of known layer-stacks with defined impedance configurations, so that developers can relate to set values and not have to develop a new layer structure every time.

Visualizing the structure in 2D (or in  3D) helps to takes the pain out of handling increasing design complexity. NB: in particularly challenging high-speed designs, it is a common (but costly) practice to order impedance-controlled printed circuit boards – as all the design constraints and calculations were made during the design. Also, please note, that impedance-controlled PCBs are not produced using higher accuracy processes; as the ‘control’ implies the creation of test coupons for all possible impedance situations on all layers and enhanced testing whether the target is met or not. Proper impedance planning early in the design phase can help save the (typically) 25% premium you’ll pay for impedance-controlled boards.

The calculation of impedances (especially when done by the formulas employed by web-based design tools) usually takes the assumption of a rectangular cross-section of the finished circuit trace with a perfect current return path. However, the real cross-section is more likely to be a polygon approaching a trapezoidal shape; sometimes crosses gaps in the reference layer underneath (current return) and can vary widely from board manufacturer to board manufacturer.

This then raises the question whether the assumption of a rectangular cross-section for an impedance calculation is accurate enough – and will signal integrity to be compromised by this non-perfectly-shaped cross-section? The field solver can take into account the etching changing the trace geometry, and they can detect situations where the track shows a so-called discontinuity as well.

As mentioned in part 1 of this blog, to ensure a reflection-free signal, high-speed nets require impedance matching. This means that the driver (output resistance), the transmission line and the receiver must show as little as possible (and ideally no) impedance difference values. In contrast, unmatched signals then show significant distortion as shown in figure 4.

However, routing may cause other issues. For instance, branches in topologies (see Figure 5) can create a voltage divider and produce therefore a reflection point – despite a supposed ideal adaptation of the same resistance in all legs (perfect matching requires we use Kirchhoff’s law for resistance in parallel).

Do you need to be 100% on target? Yes and No

In digital electronics, data and information are often exchanged point-to-point between two components. It is mandatory, that information is transmitted without being distorted or delayed.

It can be concluded that the signal integrity of critical signals must be ensured; hence, impedance control is the first step to do so. The decision of whether a signal still arrives with sufficient quality must be answered on the basis of the circuit characteristics and the component specifications. In many cases, components can detect the switching information even if the signal is slightly distorted. Alternatively, modern silicon can be programmed via hardware settings to significantly improve the signal quality at the receiver. If available, this option should always be used when working ‘close to the limits’ with regard to signal integrity budgets. Alternatives can be explored through signal integrity simulations.

To judge the effect on the signals, you must consider the two major reasons for impedance matching:

• Control the delay
• Reduce reflections and attenuation.

In the fan-out area of high-pin BGAs, traces are often ‘necked-down’ for routing space reasons between the BGA balls, which creates an impedance mismatch (i.e., a reflection situation). A typical 50Ω trace on an inner layer has a propagation delay of about 6 ns per m. If this transmission line is part of a differential pair and traverses (for instance) a BGA breakout region and has a ±30% impedance mismatch (i.e. 65Ω) over a length of 3 cm, the signal transit time will be delayed by 6ps. This will create a small phase shift even at 3GHz. Not too much of a concern. The bigger the issue is the risk of reflections.

Often, an exact adaptation of the impedance is not possible (and often unnecessary). Smaller mismatches are often still acceptable, as the proper logical switching of the signals is ensured by the semiconductors’ switching tolerances.

However, no general design rule should be inferred from this. In such cases, it is more important to minimize the deviations of the impedances – and of course to be aware of the consequences. SI simulations tools like the CR-8000 Analysis Module will reveal their virtual prototyping power in such situations.

An example of the real-life impact of matched impedance is shown in figure 6, where the switching behavior of a DDR3 data signal (point-to-point, the receiver only) is shown and where the memory vendor (Micron) demanded an impedance value of 50Ω.

During the final verification of the PCB, the designer controlled all traces of the DDR3 interface using the Zuken SI simulator, considering all possible manufacturing tolerances (20% was stated by the board manufacturer). When reaching the upper tolerance boundary of 60Ω, proper switching could not be ensured (a serious ring-back below the threshold is visible, yielding a timing error) whereas, closer to the lower boundary (between 42 and 45Ω) signal behavior is best.

This shows the strength of concurrent simulation as part of the design process and the benefits of conducting investigations on the virtual prototype.

Conclusion

For the cost-effective development of high-speed printed circuit boards, it is important to not only know the different options of impedance-controlled design but also to know (or define) the necessary and achievable tolerances.

A proven approach is to constrain up-front, design to target impedances and to optimize the PCB. The effects of an impedance mismatch must be known and understood and, in this respect, the use of simulation tools and virtual prototyping is key to success. In addition, close collaboration with the PCB manufacturer – during the early stages of your project – is highly recommended. Indeed, the CAM departments of your PCB manufacturer can often provide proper indications to solve all impedance-related design questions. However, designers are advised not to hand over the control of impedance issues to external parties.

Learn more

• Blog: Inside Signal Integrity: Impedance Control, part 1
• Zuken Blogs about Signal Integrity
• Zuken Blogs about Power Integrity

The post Inside Signal Integrity: Impedance Control – Part 2 appeared first on English.

In this, the first of a two-part blog, we’ll go back to the basics of impedance/impedance control and consider what influences line impedance. In part two, we’ll set about controlling it.

To ensure proper signal integrity for a PCB that incorporates high-speed digital devices, it is essential to control the transmission line impedance.

So, what do I mean by ‘proper signal integrity’. I refer to signal quality/purity that at the end helps to meet the timing requirements of high-speed digital devices. Increasingly, circuitry features signals with ultra-fast switching times, which must comply with ever-tightening design-constraints like skew matching or setup and hold requirements.

One of the basic constraints – the ‘mother’ of all high-speed constraints, if you will – is line impedance; be it single-ended or differential (Z_diff). Where high-speed digital ICs are concerned, the OEM or the used standard/protocol will specify the required impedance. Figure 1 shows some examples.

Alternatively, you can try to calculate the desired line impedances yourself. For this, there are a number of formulae that can be used – two of which are shown in figure 2 – that provide varying degrees of accuracy.

Common to all is that they marry your design elements (e.g., track lengths and widths, layer stacks etc) with the physical properties of the intended manufacturing process (predominantly the materials being used). Such formulae can yield esp. for single-ended structures rather accurate results – but there are not suitable for coupled situations (like differential pairs) – here more advanced techniques like field solvers are required.

For many PCB designers, dealing with impedance is their first and sometimes only contact with the complex world of high-speed design.

Transmission line impedance

The electrical behavior of a signal line is, in principle, dictated by conductor geometry. Once you know the material constants of the surrounding media, you can calculate the dielectric constant, er, which gives the electrical parameters of a line. The trace width, together with the height of the trace, determines the geometry of the trace.

Every electrical conductor comprises capacitance, inductance, and a frequency-dependent ohmic resistance (see figure 1 showing a common used electrical equivalent circuit of a transmission line segment). With increasing frequencies, the parasitics and the transmission line impedance cannot be ignored, or it will influence and may distort the signal. As a consequence, the signal becomes an active interconnect instead of a passive connection.

A change in the conductor width always means a change to the cross-sectional area and so has an impact on the maximum current and thermal behavior. In applications where very high clock speeds or data rates, and relatively long electrical line lengths are required (e.g., backplanes), ohmic resistance can also play an important role.

However, the occurrence of a change in the electrical behavior of a conductor through varying its height is relatively rare. Typical multi-layer stack-ups use conductor heights of between 17 and 36μm. These are mainly determined by mechanical constraints, such as the overall board thickness. It should be mentioned that the manufacturing process will deform the ideal rectangular (cross-sectional) shape of the track (etching effect).

Back to basics

The characteristic impedance or surge impedance (usually written Z₀) of a uniform transmission line is the ratio of the amplitudes of voltage and current of a single wave propagating along the line; that is, a wave traveling in one direction in the absence of reflections in the other direction. Characteristic impedance is determined by the geometry and materials of the transmission line and, for a uniform line, is not dependent on its length.

The standard unit (SI unit) of characteristic impedance is Ohm (W). The characteristic impedance of a lossless transmission line is purely reactive, with no real component. Energy supplied by a source at one end of such a line is transmitted through the line without being dissipated in the line itself. A transmission line of finite length (lossless or lossy) that is terminated at one end with an impedance equal to the characteristic impedance appears to the source like an infinitely long transmission line and produces no reflections. (Source: Wikipedia).

What does that mean for a PCB designer in terms of signal integrity?

It can be shown that an equivalent definition of characteristic impedance is as follows: the characteristic impedance of a line is that impedance which, when terminating an arbitrary length of the line at its output, will produce an input impedance equal to the characteristic impedance. This is so because there is no reflection on a line terminated in its own characteristic impedance (as per the above Wikipedia definition).

The characteristic impedance of a transmission line is determined by the following factors:

• The trace geometry (trace width and height);
• The distance between the signal layer and the current return path; and
• Dielectric constant, ε_r

To achieve the desired impedance and to match the required tolerances, PCB designers tend to work closely with the PCB manufacturer.

Based on the favored stack-up and the PCB layout demands, a proper impedance calculation method should be chosen. Guesswork and hope are not good engineering practices here, and the impedance targets for at least all critical signals must be determined before routing begins.

In today’s PCB manufacturing processes, tolerances of between 5 and 10% for impedance values can be achieved with: appropriate material selection; proper design of the layer stack structure (see figure 4); trace geometry planning (including any influence the etching process may have) and careful layout.

In summary, line impedance plays an even more critical role in today’s high-speed digital designs. Ideally, a transmission line should be terminated at on end with resistance in relation to its characteristic impedance to minimize signal reflections.

In part 2 of this blog, I will discuss how best to achieve line impedance control and outline the ramifications of tolerances in the manufacturing process.

Learn more

• Zuken Blogs about Signal Integrity
• Zuken Blogs about Power Integrity

The post Inside Signal Integrity: Impedance Control – Part 1 appeared first on English.

What can I tell you that’s useful? Well I hope I can help to answer some of those repeat questions, so you can concentrate on the hard stuff.

Essential facts

Fan-out and end routing

Let’s start at that differential driver on the left (). Imagine the TRUE ( ) and COMPLEMENT ( ) outputs are adjacent balls on a fine-pitch BGA, fanned-out to inner layers. Whatever else you do, keep the track lengths to fan-out vias equal, and then keep the lengths after those vias equal until you start the parallel track pattern. That parallel track pattern is the coupled section, because there’s electromagnetic coupling between the two sides.

Balance fan-out and end routing patterns separately at both ends. When you reach that receiver on the right, do the same as you did at the driver end. Don’t consider the lengths within the coupled section at all when doing this. Once TRUE and COMPLEMENT are coupled, the signals travel in a different way. I think of coupled sections as apples and fan-out and end routing as oranges – and you can’t add apples to oranges unless you want a fruit salad!

Corner angles and curves

If you only want good signal integrity, make no corner tighter than 135°. Many device application notes tell you the same. That angle works well for 45° routing. You’ll hear that curves give you better signal integrity, but for most PCB tracks – even for very fast signaling –  that isn’t true. Get curves wrong and you’ll make it a whole lot worse – and what “wrong” means isn’t always obvious.

If you’re routing on a flex, you need curves, but that’s for mechanical reasons. You have to follow mechanical constraints, so the skill there is in making sure you don’t break signal integrity in the process.

Matching to other differential pairs

Add length in coupled sections only, and keep the pair coupled all the way, because the differential impedance and delay-per-unit-length are different from the single-ended values – even within the same pair.

Matching between differential pairs and single-ended signals

In this case, you almost invariably need to add length to the pair, not the single-ended signal. As with matching between pairs, add length in coupled sections only. The application notes or standards docs will tell you how much.

Matching within a differential pair

Now you’ll remember that we matched the fan-out and end routing separately, so that’s not what I’m talking about here. This is about differences that arise within the coupled routing sections. This is sometimes called phase matching. The ideal is that TRUE and COMPLEMENT travel together in perfect complementary harmony, as shown on the left in the pictures below. There’s no such thing as perfection, so we get as close to it as we can. The faster your rising and falling edges get, the fussier phase matching requirements become. When slower edges get out of phase, the phase difference doesn’t affect the signal so much. You can see that in the pictures in the center and on the right. The phase difference matters most when TRUE or COMPLEMENT change state from low to high or high to low.

Differential impedance and delay-per-unit-length depend on phase matching. Without it, those numbers are different. To get good signal integrity, you need pretty good matching. You shouldn’t be breaking out from the coupled pattern, so the usual culprits where phase mismatches are concerned are corners. The outside track goes a bit further than the inside track.

The trap is to think you can just add the differences in length to the shorter sides, somewhere near the corners. Those are sometimes called phase bumps. There’s more to it than that, because the bump couples differently and the coupling round those corners gets quite fuzzy. You have to follow tight recommendations for exactly what those bumps should look like. If you don’t really need phase bumps, then my advice is not to add them.

The best place to start is to balance the number of 135° right and left turns and to try to minimize the number of turns. After that you can compensate for any remaining difference with a phase bump if you need to.

The real world

These PCI Express signals are making their way from a high-speed FPGA I/O bank to their connector. I guess you can see there’s a lot more to consider besides what I’ve mentioned, but I’d like to think this short blog post has helped answer a few of those golden-oldie differential-routing questions.

The post What You Really Need to Know When You’re Routing PCB Differential Pairs appeared first on English.

Overcoming Crosstalk

The higher data rates of DDR4 increase the edge rate which in turn increases the propensity for crosstalk. A general rule of thumb is to space out adjacent signal traces at least three times the trace width in order to minimize coupling effects. But it’s often difficult to implement such large trace spacing, especially on smaller PCBs such as those used in smartphones. This conundrum is increased by the fact that SDRAM uses a source synchronous clocking scheme in which all the signals in each signaling group propagate in one direction at the same time. In cases where large trace spacing cannot be achieved, the next best choice is typically to route these traces on stripline – inner PCB layers – instead of microstrip – the outer layer. This is because one side of microstrip does not have a power plane, resulting in greater dispersion of electromagnetic waves which in turn leads to a greater propensity for crosstalk to occur.

Avoiding Vias When Practical

But nothing is simple in PCB design and routing on inner layers can also create complications when DDR4 signals travel through vias from one layer of a PCB to another. Capacitance and losses in the vias can produce signal integrity problems, especially in the short stubs formed by the extension of the vias plating through to the other side of the PCB. One approach to address this problem is to minimize layer changes by routing mainly in the outer layers to avoid layer changes. But since, as mentioned earlier, routing on the outer layer increases the tendency towards crosstalk, other measures may be necessary. For example, backdrilling with numerically controlled drills to reduce the via stub length can significantly lower the bit error rate of the interconnect.

Tune the Silicon to the Board

Cases where designers have control over the silicon provide an additional avenue to address potential DDR4 problems. Devices such as field programmable gate arrays (FPGAs) enable engineers to move pins around to reduce trace lengths. While ICs, packages and PCBs are typically designed with point tools whose interface requires time-consuming manual processes, a new integrated 3D chip/package board co-design environment enables engineers to see the IC, package and PCB simultaneously in one view to optimize tradeoffs between the pin placement and PCB routing, among other things. This new approach makes it much easier to, for example, swap pins between banks, to achieve better length control.

The post A Few Thoughts on Avoiding DDR4 Layout Problems appeared first on English.

Measuring S-Parameters

S-Parameters represent the transmission and reflection of waves at a specific frequency, when the network is embedded within long transmission lines with a specific load. These models are automatically adapted for use with different loads. S-Parameter models, in formats such as Touchstone, state the load as which the parameters were measured.

Figure 2: Two-Port Network Embedded within Transmission Lines

S₂₁ and S₁₁ can be measured by embedding the component to be modelled within a test circuit where the load impedance matches characteristic transmission line impedance. In this way there is no reflection from the far end, so there is no input signal a₂ at Port 2. To find S₁₂ and S₂₂, the connections are reversed.

For instance the measured voltages and derived S11 and S21 for a 2-port network comprising a 200mm length, 100Ω transmission line with negligible loss at 250MHz are shown in Figure 4.

Measured Voltages for S-Parameter Model of 200mm Transmission Line

In practice, you would need frequency samples covering the applicable range, but for illustration, Figure 5 is a Touchstone format extract containing entries for just two frequency points: the 250MHz parameters I have just derived, and another at 200MHz. This transmission line constitutes a symmetrical network, so S₁₁=S₂₂ and S₁₂=S₂₁.

In real life, S-Parameters will mostly be used for components such as filters and connectors, but the measurement technique and format of the model remains the same.  Two requirements commonly apply to S-Parameter models used in high-speed PCB design:

1. Passivity – The model must not generate more energy that is supplied to it. A passive filter or a connector cannot exhibit gain.
2. Causality – Determination of causality is more complex, but basically, the response of the model must depend only on its current and previous inputs. This will always be the case with a correctly constructed passive filter or connector model.

Simulation with S-Parameter Models

Most simulation of high-speed digital circuits is performed by time-domain simulators that work in conjunction with design capture and physical layout.

The system used to illustrate this series of posts is our CR-5000 Lightning software, used by many consumer electronics, industrial and aerospace companies to design high-end printed circuit boards.

S-Parameter models describe the response at a range of frequencies rather than in the time domain, so they are first transformed into compatible macro-models by importing them into the simulation library via IdEM.

A common-mode filter is sometimes employed in high-speed differential buses such as USB to reduce off-board conducted Electromagnetic Interference (EMI).  Differential signals comprise two complementary parts that, ideally, are always exactly opposite in phase. Signals that are in-phase, therefore, can be assumed to be unwanted noise.

Figure 6: USB Common Mode Filter

Since differential PCB traces are usually routed nearby and in parallel, in-phase noise is often picked up on both sides of the differential pair. The purpose of the Common Mode filter in Figure 6 is, as far as possible, to suppress this noise while allowing the differential signal through.

Figure 7 and Figure 8 show confirmation of the effectiveness of this kind of filter using simulation. Crosstalk from a closely-coupled, 1V peak amplitude, 100MHz sine wave signal has been induced equally on the + and – sides of the differential pair.

In the ideal differential signal, the + (shown in red) and – (shown in blue) waveforms would be exactly opposite in phase. Crosstalk from the 100MHz sine wave, coupled equally to each side of the pair, is in-phase on the two sides. The crossing points of the + and – waves should ideally be central, but the noise has broken this symmetry.

Figure 8: Differential Pair with Filtered In-Phase Noise

After filtering, the noise has been greatly reduced, and the crossing points have become more central.

Summary

With each large increment in bit rate comes a new set of high-speed issues, so that simulation techniques previously only required for RF and microwave applications have to be incorporated into mainstream PCB design flows. You might be experiencing the pressure yourself to start dealing with these issues.

The good thing is, S-Parameters allow accurate modelling of component behaviour without revealing the internal structure and can be derived by measurement alone. The ability to simulate S-Parameter models enhances the accuracy of EDA software for high-speed digital PCB design.

What is your experience, are you being forced to become a high-speed design expert?

Maybe you want to share your design ideas on the topic? Send me a comment and let’s talk about it.

• Read previous post: S-Parameters: Microwave goes Mainstream for High-Speed PCB Design Part 1

The post S-Parameters: Microwave goes Mainstream for High-Speed PCB Design Part 2 appeared first on English.

So here goes. Mainstream high-speed PCB design has generally followed in the slipstream of RF and microwave engineering. This is often out of necessity, as techniques have been simplified and made applicable to wider use. For example IBIS models that describe input/output behaviour without revealing internal design details are published for most high-speed integrated circuits.

And we all know double data rate memory has become the de facto standard for PC-based designs. This has turned the design of every board that uses it into a high-speed electronic engineering exercise – often involving system-level and multi-board interconnect.

For high-speed differential channels, such as USB, signal-enhancing components such as common-mode filters are often involved. At today’s bit rates, simple RLC models of such components do not fit the bill, but neither do models that require deep analysis of the physical structures. What is needed is a technique that, as in IBIS, reveals the minimum amount of information about the internal structure while describing the interface sufficiently to simulate it accurately at frequencies into the multi-Gigahertz range.

Luckily, such a technique is ready and waiting: S-Parameters.

I’d like to explain to you in straightforward terms what S-Parameters are and why they’re so useful. When I say “straightforward”,  I mean that in a technical sense, but this is a specialised area. If you’re not designing high-speed PCBs, or you don’t know much about signal integrity, you might want to tune out now.

For the purpose of simplicity, I’ll limit all the discussion to two-port networks.

What S-Parameters Represent

Let’s start with a definition.

S-Parameters are Scattering Parameters: they describe how derivatives of a wave arriving at a circuit network port are scattered to all of the ports, including the one at which the wave arrived. Each S-Parameter names the port to which the wave is scattered first, followed by the port from which it has been scattered. S₂₁, therefore, is the S-Parameter for the wave scattered to Port 2 from Port 1, representing the transformation in terms of both magnitude and phase.

Let me show you an example to illustrate what I mean. S-Parameters are used in high-frequency electronics circuits, but first imagine that you wanted to describe the behaviour of a lens as shown in Figure 1.  This is useful because in the lens, as in high-speed circuits, we are concerned with both transmission and reflection, and the lens is easier to visualise.

Figure 1: Lens Analogy

At high frequencies, the behaviour of a lens is analogous to that of a high-speed circuit such as a filter

You could analyse the physical properties in detail to predict the transmission and reflection of light at various frequencies. But this a complex task, and if you failed to take account of more subtle effects, your result might not be accurate.

An alternative approach would be to treat the lens as a black box, and merely measure its behaviour at various frequencies.

Let a₁ and a₂ be the incident waves on the left-hand (Port 1) and right-hand (Port 2) sides of the lens respectively.

At each individual frequency, we need to know:

1. The amplitude and phase shift of light transmitted from Port 1 to Port 2.  Let S₂₁ represent this transformation, so that the output at Port 2 given input a1 at Port 1 is S₂₁a₁.
2. The amplitude and phase of light reflected from Port 1 for input a₁.  Let S₁₁ represent this transformation, so that the reflection at Port 1 is S₁₁a₁.
3. The same information as in 1), but for light transmitted from port 2 to port 1 (S₁₂a₂).
4. The same information as in 2), but for light reflected from port 2 (S₂₂a₂).

OK, time for a short video clip. This is a two-port network – it could be a connector or a filter – and this is what happens to a sine wave at just one frequency, described as S-Parameters. An S-Parameter model contains a set of parameters for a large number of frequencies that cover the frequency content of a fast digital signal.

At Port 1 and Port 2, the final results (b1 and b2 respectively) are the sum of the transmitted and reflected waves, so that, expressed in matrix form:

The items in the matrices include magnitude and phase, and can be expressed either as complex numbers or as magnitude and phase angle.

Like visible light, digital electronic signals contain a range of frequencies at various amplitudes and phase angles.  If we know S₁₁, S₁₂, S₂₁ and S₂₂ for a range of frequencies within the limits of operation, we have the means to simulate a circuit such as a filter without the need to know the internal structure, and making no assumptions that might affect simulation accuracy.

S₂₁ is the forward voltage transmission coefficient, because if you multiply the incident AC voltage at Port 1 by S₂₁, you get the voltage transmitted to Port 2.

S₁₁ is the input voltage reflection coefficient, because if you multiply the incident AC voltage at Port 1 by S_11, you get the voltage reflected from Port 1.

• See part 2 which details how to measure S-Parameters and simulate with S-Parameter models. You can also find out about what technology from Zuken supports this, please go to the CR-5000 Lightning web pages.

The post S-Parameters: Microwave goes Mainstream for High-Speed PCB Design Part 1 appeared first on English.